Multiplexed and interlaced charge-coupled serial-parallel-serial memory device

ABSTRACT

An interlaced charge-coupled serial-parallel-serial memory device unscrambles the scrambled bit sequence produced by conventional interlacing, so that the output serial data bit stream has the same original bit sequency as the input bit stream.

BACKGROUND OF THE INVENTION

1. Field of the Invention

This invention relates generally to interlaced serial-parallel-serialcharge-coupled memory devices, and more particularly, to a novelarrangement which outputs the serial data bit stream in the sameoriginal sequence as the input bit stream.

2. Description of the Prior Art

Interlaced serial-parallel-serial memory devices for use in dataprocessing system storage and communication signal processing arewell-known in the art. Referring to the patents and publications listedbelow under the heading "References Cited By Applicant", Boyle and Smith[Refs. 1, 2, 3] originally disclosed the basic charge-coupled concept.Weimer [Ref. 4], Tompsett [Ref. 5] and Collins [Ref. 6] disclosedserial-parallel-serial arrangements.

In the serial-parallel-serial configuration, a data bit stream isinjected into a serial input shift register from where it is transferredin parallel to a parallel storage section. The data can then be shiftedin parallel through the parallel section, and then transferred inparallel to a serial output register, from where it is shifted out as aserial bit stream.

This serial-parallel-serial configuration had bit density limitationsbecause charge-coupled devices require both transfer and storage sites.That is, in a two-phase serial shift register, the storage of one bit ofinformation requires not only a storage site but also a transfer site sothat bits are actually stored at one instant of time in only one-half ofthe available sites. For example, in a two-phase serial charge-coupleddevice with eight sites, only four bits can be stored. The parallelsection was similarly limited in that the channel width was necessarilytwice the width of a single site in the serial sections so that onlyone-half of the potentially available storage sites in the parallelsection could be utilized.

Bit storage density was then significantly improved by the interlacedmodification of the serial-parallel-serial configuration. In aninterlaced version of the above example having eight sites and two-phaseoperation, all eight serial bits can be transferred in parallel throughthe parallel section, at least theoretically doubling the number of bitsthat can be stored in the parallel section. Embodiments of interlacedconfigurations are disclosed by Elmer et al. [Ref. 10, 11, 12],Kosonocky [Ref. 8, 9], and Erb [Ref. 7].

However, the interlaced configuration of the prior art had the seriousdisadvantage that the data bits were scrambled upon transfer from theserial input register into the first row of the parallel section. Thatis, the data bits were put in a sequential order different from theoriginal order of the input bit stream. It was then necessary to provideadditional circuitry to unscramble the bits and put them back into theoriginal sequential order. This additional circuitry substantiallyincreased the complexity and cost of the interlaced devices.

SUMMARY OF THE INVENTION

It is therefore a primary object of the present invention to provide anovel interlaced serial-parallel-serial configuration which outputs thedata bits in the same sequential order as the original order of theinput bit stream.

A further object is to provide this unscrambled output bit stream bymeans of circuitry which is less complex and less expensive than theunscrambling schemes of the prior art.

In the preferred embodiment disclosed for purposes of illustrating oneof the many forms which the invention may take in practice, theseobjects are achieved by a novel combination of twoserial-parallel-serial loops. The alternate odd bits of a first recordof the input bit stream are interlaced with the alternate even bits ofanother record of the input stream and these interlaced bits are storedin the first serial-parallel-serial loop. Similarly, the alternate evenbits of the first record are interlaced with the alternate odd bits ofthe other record and these interlaced bits are stored in the secondserial-parallel-serial loop. By properly timed clock signals theinterlaced bits may then be alternately transferred out of theserial-parallel-serial loops in the same original sequence as the inputbit stream.

IN THE DRAWINGS

FIGS. 1 to 6 inclusive illustrate the problem of scrambled data bitsinherent in the interlaced serial-parallel-serial configurations of theprior art.

FIG. 7 shows a pair of serial-parallel-serial loops and associatedcontrol logic in accordance with the present invention.

FIG. 8 shows details of the conventional control logic indicatedsymbolically in FIG. 7.

FIG. 9 shows the data bit sequence in the serial input section of thefirst loop in accordance with the present invention wherein thealternate odd bits of a first record are interlaced with the alternateeven bits of a second record.

FIG. 10 is similar to FIG. 9 but shows the bit sequence of the serialinput section of the second loop wherein the alternate even bits of thefirst record are interlaced with the alternate odd bits of the secondrecord.

FIG. 11 shows the original and final data bit sequence of a firstrecord.

FIG. 12 shows the original and final data bit sequence of another recordwhich is interlaced with the first record in the two loops.

DETAILED DESCRIPTION

Referring first to FIGS. 1 to 6 inclusive, there is shown the scrambleddata bit effect produced by conventional interlacedserial-parallel-serial configurations in accordance with the prior art,in order to illustrate the problem obviated by the present invention. Ineach of these figures the serial input register section is indicated atS and the parallel section is indicated at P. Only the first two rows ofthe parallel section P are shown. For simplicity and clarity inillustration, the serial input section S is shown as having only eightcharge packet storage sites, and the parallel section is shown as havingonly eight columns each associated with a respective one of the serialsection sites. It will be understood that in a production embodimentboth sections may have many more sites and columns, respectively.

Referring to FIG. 1, the first four data bits of a serial bit stream aredesignated 1 to 4 respectively and are shifted serially into the serialinput section S as shown. Each bit is transferred to the first storagesite by the input clock signal φ1. The serial transfer of the chargepackets corresponding to the respective bits is achieved by conventionalclock signals φA and φB. It will be understood that the clock signalsφA, φB, φ1, φ1', φ2' shown in FIG. 1 are also operative in FIGS. 2 to 6inclusive, although not shown to avoid unnecessary duplication.

As viewed in FIG. 2, the clock signal φ2' causes the four charge packetscorresponding to the first four data bits 1, 2, 3, 4 to be transferredsimultaneously in parallel into the first row of the parallel section P.It will be seen that the charge packets corresponding to the first fourdata bits occupy alternate charge storage sites in the first row of theparallel section P.

Referring now to FIG. 3, the first four data bits 1, 2, 3, 4 have beentransferred by clock signal φ1' into the second row of the parallelsection P while the charge packet corresponding to the fifth data bitdesignated at 5 has been shifted into the first charge storage site ofthe serial input section S. Referring now to FIG. 4 the second group offour bits designated as 5, 6, 7, 8 have been shifted serially intoserial input section S by the clock signals φA and φB. It will be seenthat these bits 5, 6, 7, 8 occupy the alternate charge storage siteswhich were not occupied by the first group of bits 1, 2, 3, 4.

In FIG. 5 the second group of four data bits 5, 6, 7, 8 have beenshifted by clock signal φ2' from the serial input section S into thefirst row of the parallel section P, while simultaneously the ninth databit has been input into the first charge storage site of serial sectionS. In FIG. 6 the clock signal φ1' has transferred the second group ofdata bits 5, 6, 7, 8 from the first row of parallel section P into thesecond row.

It will be seen that the first group of data bits 1, 2, 3, 4 and thesecond group of data bits 5, 6, 7, 8 are now interlaced in the secondrow of parallel section P and that the bit sequence has been scrambledso as to differ from the original sequence. In accordance with the priorart, this scrambled bit sequence in the order 5, 1, 6, 2, 7, 3, 8, 4 wasthen transmitted in parallel from row to row of the parallel section Pand was then unscrambled upon output from the last row of the latter. Asheretofore practiced in the prior art, this unscrambling function hasrequired additional logic circuitry which is complex and expensive.

Referring now to FIG. 7, there is shown a preferred embodiment of theinvention. A first serial-parallel-serial configuration LOOP 1 comprisesa serial input section SI1, a parallel section P1, a serial outputsection S01, and a regenerator R1. A line 4 extends from regenerator R1to the input of serial input Section SI1. A line 6 extends from theoutput of serial output section S01 to regenerator R1.

A second serial-parallel-serial configuration LOOP 2 comprises a serialinput section SI2, a parallel section P2, a serial output section SO2,and a regenerator R2. A line 5 extends from regenerator R2 to the inputof serial input section SI2. A line 7 extends from the output of serialoutput section SO2 to the regenerator R2.

Data is input and output from the configuration by means of aconventional input/output interface L2 and having an input port DATA INand an output port DATA OUT. Lines 1, 2, extend from the input/outputinterface L2 to regenerator R1, and lines 1, 3 similarly extend toregenerator R2.

The address decoding logic and the logic for LOOP timing and selectionof the alternate odd and even bits of the respective data records aresymbolically designated by a logic block L1 having an input port addressfor address selection. A line 8 extends from the address decoder logicL1 to a first AND gate A1, and a second line 9 extends to a second ANDgate A2. The other input of AND gate A1 is connected to a line 7extending from regenerator R2, and the other input of AND gate A2 isconnected to a line 6 extending from regenerator R1.

It will be understood that the logic for data regeneration, addressdecoding, LOOP bit selection and timing, and input/output interfacinghas been subdivided into the four logic block symbols R1, R2, L1, L2,shown in FIG. 7 for purposes of clarity in illustration, and that inactual practice the circuitry for performing these logic functions isintimately interconnected rather than disassociated into separatediscrete logic blocks as shown in the drawing. Furthermore, thiscircuitry is conventional and well-known in the art and the detailsthereof form no part of the present invention. In order to illustrateone of the many forms which circuitry of this type may take in practice,FIG. 8 shows a typical conventional arrangement for controlling theinput, output, read and write operations of serial-parallel-serialconfigurations.

For simplicity and clarity in illustration, there are shown in FIG. 8only three serial-parallel-serial configurations designated respectivelyas LOOP 1, LOOP 2, and LOOP N. The three loops shown are identical andhave applied thereto the same reference numerals with the suffix "1"applied to LOOP 1, the suffix "2" applied to LOOP 2, and the suffix "N"applied to LOOP N. Therefore only LOOP 1 will be described in detail.

LOOP 1 comprises a serial input register section SI1, a parallel sectionP1 and a serial output register section SO1. Associated with LOOP 1 arelogic gates including three AND gates A11, A21, A31, an OR gate O1, aninverter I1, an input device ID1, and an amplifier AM1. Each of theselogic elements is conventional.

The input data is applied where indicated by the legend in the drawingand is transmitted to one input of each of the AND gates A11, A12, A1N.The second input of AND gate A11 has applied thereto an enable signaldesignated LOOP 1 ENABLE. Similarly, each second input of AND gates A12and A1N have applied thereto enable signals respectively designated inthe drawing. The third input of each of the AND gates A11, A12, A1N hasapplied thereto the output signal of AND gate A5. One of the inputs ofthe latter receives the WRITE COMMAND signal and its other inputreceives the READ WRITE ENABLE signal.

The output signal of AND gate A5 is also transmitted to the inputs ofthe respective inverters I1, I2, IN. The outputs of the latter aretransmitted to the respective AND gates A21, A22, A2N. The outputs ofthe latter are transmitted to the respective inputs of OR gates O1, O2,ON. The outputs of the latter are in turn transmitted to the respectiveinput devices ID1, ID2, IDN.

The outputs of the serial output register sections SO1, SO2, SON aretransmitted to the respective inputs of amplifiers AM1, AM2, AMN. Theoutputs of the latter are transmitted to the respective AND gates A21,A22, A2N. The outputs of amplifiers AM1, AM2, AMN are also transmittedto the inputs of the respective AND gates A31, A32, A3N. The LOOP ENABLEsignals are also transmitted to the latter gates. The outputs of ANDgates A31, A32, A3N are transmitted to the respective inputs of OR gateO3 having its output transmitted to one of the inputs of AND gate A4.The second input of the latter has applied thereto the READ WRITE ENABLEsignal, and its third input has applied thereto the READ COMMAND signal.The output of AND gate A4 provides the OUTPUT DATA signal.

OPERATION

The operation of the present invention will now be described withreference to FIGS. 7 and 9 through 12 inclusive. The serial data bitstream is transmitted to the DATA IN port of I/O INTERFACE L2. Forsimplicity and clarity in illustration, it will be assumed that thisserial input stream comprises a sequence of data records each consistingof a train of eight bits. The two loop configurations LOOP 1 and LOOP 2shown in FIG. 7 function to store two such data records. These recordsare generally not contiguously located in the input data bit stream. Thebits of the first record will be designated as A1 through A8, and thebits of the second record will be designated as X1 through X8.

By clock signals applied to the control logic circuitry, the alternateodd bits A1, A3, A5, A7 are transmitted from the I/O INTERFACE L2 alonglines 1, 2 to the regenerator R1 and then by line 4 to the serial inputsection SI1 of LOOP 1. In a similar manner, the alternate even bits X2,X4, X6, X8 of the data bit stream are transmitted to the serial inputsection SI1 of LOOP 1 and are interlaced in said serial input sectionwith the previously transmitted alternate odd bits A1, A3, A5, A7 of thefirst record, to provide in the serial input secton SI1 of the firstloop the bit sequence shown in FIG. 9. This row of bits is thentransmitted in parallel through parallel section P1 of LOOP 1 in theconventional manner.

The alternate even bits A2, A4, A6, A8 of the first record of the serialdata bit stream are transmitted by timed clock signals from I/OINTERFACE L2 through lines 1, 3, regenerator R2 and line 5 to the serialinput section SI2 of LOOP 2. In a similar manner the alternate odd bitsX1, X3, X5, X7 of the second record are transmitted to said serial inputsection SI2 of LOOP 2 and are interlaced with the even bits A2, A4, A6,A8 previously transmitted so as to provide in serial SI2 the bitsequence shown in FIG. 10. This row of bits is then transmitted inparallel through parallel section P2 of LOOP 2 in the conventionalmanner.

The row of bits shown in FIG. 9 eventually reaches the serial outputregister section SO1 of LOOP 1, and the row of bits shown in FIG. 10eventually reaches the serial output register section SO2 of LOOP 2. Therow shown in FIG. 9 may then be either regenerated by regenerator R1 andtransmitted back through line 4 to the input of serial input sectionSI1, or instead may be transmitted through line 6 and AND gate A2 to theI/O INTERFACE L2 for output at the DATA OUT port. Similarly, the row ofdata bits shown in FIG. 10 eventually reaches serial output registersection SO2 and then may either be regenerated in regenerator R2 andtransmitted back through line 5 to the serial input register sectionSI2, or alternatively may be transmitted through line 7 to AND gate A1for output at the DATA OUT port.

By appropriately timing the clock signals the sequential order of thebits transmitted at the DATA OUT port may be readily selected so as tooutput the bits of the first record in their original sequence as shownin FIG. 11 and the bits of the second record in their original sequenceas shown in FIG. 12. The address decoders odd/even timing and LOOPselector logic indicated symbolically at L1 provides suitable timingsignals to AND gates A1, A2 so as to gate the I/O INTERFACE at L2 at theproper instant and to output the bits of the respective records in theiroriginal sequence shown in FIGS. 11 and 12, or in any other arbitrarysequence as may be desired.

While the invention has been shown and particularly described withreference to a preferred embodiment, it will be understood by thoseskilled in the art that various changes in form and detail may be madetherein without departing from the scope of the invention which isdelineated in the appended claims.

REFERENCES CITED BY APPLICANT

1. boyle, W. S. and Smith G. E., "Charge Coupled Semiconductor Devices,"Bell Sys. Tech. J. (April 1970) pp. 587-593.

2. Boyle, W. S. and Smith, G. E., U.S. Pat. No. 3,858,232; issued Dec.31, 1974; filed Nov. 9, 1971.

3. Smith, G. E., U.S. Pat. No. 3,761,744; issued Sept. 25, 1973; filedDec. 2, 1971.

4. Weimer, P. K., U.S. Pat. No. 3,763,480; issued Oct. 2, 1973; filedOct. 12, 1971.

5. Tompsett, M. F., "Charge Transfer Devices," J. Vac. Sci. Technol.,Vol. 9, No. 4, (July-August 1972) pp. 1166-1181.

6. Collins, D. R., Barton, J. B., Buss, D. C., Kmetz, A. R., andSchroeder, J. E., "CCD Memory Options," 1973 IEEE InternationalSolid-State Circuits Conference, (February 1973) pp. 136-137, 210.

7. Erb, D. M., U.S. Pat. No. 3,913,077; issued Oct. 14, 1975; filed Apr.17, 1974.

8. Carnes, J. E. and Kosonocky, W. F., "Charge-Coupled Devices andApplications," Solid State Technology, (April 1974) pp. 67-77.

9. Kosonocky, W. F. and Sauer, D. J., U.S. Pat. No. 3,967,254; issuedJune 29, 1976; filed Nov. 18, 1974.

10. Elmer, B. R., Tchon, W. E., Denboer, A. J., Frommer, R., Kohyama, S.and Hirabayashi, K. "Fault Tolerant 92160 Bit Multiphase CCD Memory,"IEEE International Solid-State Circuits Conference (February 1977) pp.116-117.

11. Elmer, B. R., U.S. Pat. No. 4,024,509; issued May 17, 1977; filedJune 30, 1975.

12. Elmer, B. R. and Tchon, W. E., U.S. Pat. No. 3,986,179; issued Oct.12, 1976; filed June 30, 1975.

What is claimed is:
 1. A charge-coupled memory device comprisinga firstserial-parallel-serial loop including a first serial input section, afirst parallel section and a first serial output section, a secondserial-parallel-serial loop including a second serial input section, asecond parallel section and a second serial output section, input meansfor receiving a serial data bit stream including a first recordcomprising a first serial train of bits and a second record comprising asecond serial train of bits, first clocking means for transmitting thealternate odd bits of said first record to said first serial inputsection, second clocking means for transmitting the alternate even bitsof said first record to said second serial input section, third clockingmeans for transmitting the alternate even bits of said second record tosaid first serial input section, fourth clocking means for transmittingthe alternate odd bits of said second record to said second serial inputsection, means for converting said bits into charge packets, and meansfor transferring the respective charge packets through said first andsecond serial input sections, then through said first and secondparallel sections and then through said first and second serial outputsections.
 2. A charge-coupled memory device as recited in claim 1 andcomprisingoutput means, means transmitting said bits from said serialoutput sections to said output means, said output means including fifthclocking means for transmitting said bits of said first record in thesame sequential order as said first serial train and for transmittingsaid bits of said second record in the same sequential order as saidsecond serial train.
 3. A charge-coupled memory device as recited inclaim 1 whereinsaid first and second clocking means include means forinterlacing in said first parallel section said odd bits of the firstrecord with said even bits of the second record, and said third andfourth clocking means include means for interlacing in said secondparallel section said even bits of the first record with said odd bitsof the second record.
 4. A charge-coupled memory device as recited inclaim 1 and comprisingoutput means, means transmitting said bits fromsaid serial output sections to said output means, said output meansincluding fifth clocking means for transmitting said bits of said firstrecord in the same sequential order as said first serial train and fortransmitting said bits of said second record in the same sequentialorder as said second serial train, said first and second clocking meansincluding means for interlacing in said first parallel section said oddbits of the first record with said even bits of the second record, andsaid third and fourth clocking means including means for interlacing insaid second parallel section said even bits of the first record withsaid odd bits of the second record.
 5. A charge-coupled memory devicecomprisinga plurality of serial-parallel-serial loops each including aserial input section, a parallel section and a serial output section,input means for receiving a serial data bit stream including a pluralityof records each comprising a serial train of bits having an originalpredetermined sequential order, means for transmitting a first set ofbits of one record to one of said serial input sections, means fortransmitting a second set of bits of said one record to another of saidserial input sections, means for transmitting a first set of bits ofanother record to said another serial input section, means fortransmitting a second set of bits of said another record to said oneserial input section, means for converting said bits into chargepackets, and means for transferring the respective charge packetsthrough said serial input sections, then through said parallel sectionsand then through said serial output sections.
 6. A charge-coupled memorydevice as recited in claim 5 and comprisingoutput means, meanstransmitting said bits from said serial output sections to said outputmeans, said output means including means for transmitting said bits ofsaid one record in the same sequential order as the originalpredetermined order thereof and for transmitting said bits of saidanother record in the same sequential order as the originalpredetermined order thereof.
 7. A charge-coupled memory device asrecited in claim 5 whereinsaid transmitting means include means forinterlacing in one of said parallel sections said first set of bits ofsaid one record with said second set of bits of said another record, andsaid transmitting means include means for interlacing in said anotherparallel section said second set of bits of said one record with saidfirst set of bits of said another record.
 8. A charge-coupled memorydevice as recited in claim 5 and comprisingoutput means, meanstransmitting said bits from said serial output sections to said outputmeans, said output means including means for transmitting said bits ofsaid first record in the same sequential order as the originalpredetermined order thereof and for transmitting said bits of saidanother record in the same sequential order as the originalpredetermined order thereof, said transmitting means including means forinterlacing in one of said parallel sections said first set of bits ofsaid one record with said second set of bits of said another record, andsaid transmitting means including means for interlacing in said anotherparallel section said second set of bits of said one record with saidfirst set of bits of said another record.
 9. A charge-coupled memorydevice comprisinga first serial-parallel-serial loop, a secondserial-parallel-serial loop, input means for receiving a serial data bitstream including one record comprising one serial train of bits and adifferent record comprising a different serial train of bits, clockingmeans for transmitting the alternate odd bits of said one record to saidfirst loop and for transmitting the alternate even bits of said onerecord to said second loop, clocking means for transmitting thealternate even bits of said different record to said first loop and fortransmitting the alternate odd bits of said different record to saidsecond loop, said clocking means including means for interlacing in saidfirst loop said odd bits of said one record with said even bits of saiddifferent record, said clocking means including means for interlacing insaid second loop said even bits of said one record with said odd bits ofsaid different record, output means, means transmitting said bits fromsaid loops to said output means, said output means including clockingmeans for transmitting said bits of said one record in the samesequential order as said one serial train and for transmitting said bitsof said different record in the same sequential order as said differentserial train.